GNU Make

The specification that make uses is generally saved in a file named makefile.

The specification file, or makefile, describes the relationship between the source, intermediate, and executable program files so that make can perform the minimum amount of work necessary to update the executable.

If a target is included as a command-line argument, that target is updated. If no command-line targets are given, then the first target in the file is used, called the default goal.

Essentially a makefile contains a set of rules used to build an application. The first rule seen by make is used as the default rule. A rule consists of three parts: the target, its prerequisites, and the command(s) to perform:

target: prereq1 prereq2

    commands

The target is the file or thing that must be made. The prerequisites or dependents are those files that must exist before the target can be successfully created. And the commands are those shell commands that will create the target from the prerequisites.The command script usually appears on the following lines and is preceded by a tab character.

Each command must begin with a tab character. This (obscure) syntax tells make that the characters that follow the tab are to be passed to a subshell for execution.

Long lines can be continued using the standard Unix escape character backslash (\). It is common for commands to be continued in this way. It is also common for lists of prerequisites to be continued with backslash.

Variables

In general, a variable name must be surrounded by $( ) to be recognized by make. As a special case, a single character variable name does not require the parentheses.

Automatic variables are set by make after a rule is matched. They provide access to elements from the target and prerequisite lists so you don't have to explicitly specify any filenames.

There are six "core" automatic variables:

$@ The filename representing the target.

$% The filename element of an archive member specification.

$< The filename of the first prerequisite.

$? The names of all prerequisites that are newer than the target, separated by spaces.

$^ The filenames of all the prerequisites, separated by spaces. This list has duplicate filenames removed since for most uses, such as compiling, copying, etc., duplicates are not wanted.

$+ Similar to $^, this is the names of all the prerequisites separated by spaces, except that $+ includes duplicates. This variable was created for specific situations such as arguments to linkers where duplicate values have meaning.

$* The stem of the target filename. A stem is typically a filename without its suffix. Its use outside of pattern rules is discouraged.

Finding files with VPATH and vpath

By default, make will look in the current directory for its targets and prerequisites.
MAKE and GCC have different search path! (有各自独立的搜索路径!)

-I dir
          Add the directory dir to the list of directories to be searched for
          header files.  Directories named by -I are searched before the
          standard system include directories.  If the directory dir is a
          standard system include directory, the option is ignored to ensure
          that the default search order for system directories and the spe‐
          cial treatment of system headers are not defeated .

for source files: VPATH = src1:src2:src3;
make will search src folder if it can not find the file in the current directory.
modify the implicit compilation rule for header files: CPPFLAGS = -I include

In general, it is good to use variable name to represent external programs.